This invention relates generally to the field of semiconductor devices, and more particularly to an improved method for forming a self-aligned contact.
In the art of field effect transistor (FET) fabrication, it is often desirable to perform processes which are self-aligning. For example, techniques for implanting self-aligned source and drain pockets in a substrate after a gate has been deposited on the substrate are well known.
In addition, a technique for forming a self-aligned contact to a source or drain pocket has been established. This technique typically involves forming an insulating shield layer of silicon nitride over and around the gate. Another insulator layer of silicon dioxide is then deposited on the gate and substrate. A hole is then patterned and etched into the silicon dioxide layer, forming a self-aligned contact well that adjoins the silicon nitride barrier layer and exposes an area of the source or drain pocket. A contact material may then be deposited in the contact well to form an electrical contact to the source or drain pocket.
Formation of a self-aligned source or drain contact using the above-described technique requires, in the contact well formation step, an etchant that removes silicon dioxide but is selective against silicon nitride. The etchant typically used for this purpose is carbon monoxide gas, which is hazardous to store and dispose of due to its poisonous nature.
Moreover, the relatively high dielectric constant of the silicon nitride layer surrounding the gate results in a high parasitic gate capacitance. Consequently, a FET fabricated according to this technique exhibits the undesirable properties of high power consumption and low switching speed.
Therefore, a need has arisen for a method for forming a self-aligned contact that addresses the disadvantages and deficiencies of the prior art.
An improved method for forming a contact well for a semiconductor device is disclosed. In accordance with this method, a first insulator layer comprising an insulating material is formed around a gate. A contact well filler is then formed adjoining the first insulator layer. A second insulator layer comprising the insulating material is formed around the first insulator layer and the contact well filler. The contact well filler is then removed to form the contact well in the second insulator layer.
A technical advantage of the present invention is that a non-hazardous selective etchant may be used to form the contact well. Another technical advantage is that the semiconductor device formed in accordance with the present invention exhibits low parasitic gate capacitance, high switching speed and low power consumption.